Professor Souvik Mahapatra
Department of Electrical Engineering
Indian Institute of Technology, Bombay
Trap generation and charge trapping in the gate insulator of a MOSFET due to Bias Temperature Instability (BTI) result in drift of transistor parameters and eventually cause circuit/product failure. The underlying physical mechanisms of these processes are now understood and modelled using partial differential equations (PDEs) for large area devices, where “average” behavior is observed. Such a framework can explain BTI kinetics for planar, FDSOI and FinFET technologies. However, present day devices are smaller in area and one can have a handful of defects, which should be handled by a stochastic framework. In this talk, we will discuss the development of KMC-based stochastic trap generation and trapping formalisms and verify their robustness against macroscopic PDE formalisms and experimental data. The shape of the distribution, and the time kinetics of mean and variance of experimental data would be predicted.
Souvik Mahapatra received his PhD from IIT Bombay in 1999. During 2000-01, he was with Bell Laboratories, Murray Hill, NJ. Since 2002, he has been with the Department of Electrical Engineering at IIT Bombay and is presently a full professor. His current research interests are CMOS device scaling and reliability, and device-circuit co-design for co-optimization of power, performance, and reliability. He has published more than 150 papers in peer reviewed journals and international conferences, delivered invited talks at major international conferences, including IEEE IEDM and IRPS, and has been actively collaborating with several global semiconductor industries. He is a fellow of IEEE (for contributions to CMOS transistor gate stack reliability), a fellow of INAE, and a distinguished lecturer of the IEEE Electron Devices Society.
Originally published at nano.nd.edu.